A storage apparatus generally has a storage controller and a randomly accessible nonvolatile storage medium. This storage medium is, for example, a disk array including multiple hard disk drives (HDDs) or nonvolatile semiconductor memory drives (SSD: solid state drives).
The storage controller includes a front-end interface (FEIF) for connecting a higher-level apparatus (such as a host system), a back-end interface (BEIF) for connecting the disk array, and a cache memory (CM) for temporarily storing data which the higher-level apparatus reads from and writes to the disk array, and an interface (CMIF) for the CM. The storage controller further has a processor for controlling data transfer between the host system and the CMIF and between the disk array and the CMIF.
As a communication network standard specification for connecting a processor with an FEIF, a BEIF and the like, “PCI Express” is known. As extended specifications of the PCI Express, “Single-Root I/O Virtualization and Sharing Specification” (hereinafter “SR-IOV”), which is a standard specification for an I/O device compatible with the PCI Express to support virtualization, and “Multi-Root I/O Virtualization and Sharing Specification” (hereinafter “MR-IOV”), which is a standard specification for multiple processors to share an I/O device, are known.
By an endpoint (hereinafter “EP”), which is an I/O device, having at least one physical function (PF), an apparatus in conformity with the SR-IOV specification can provide multiple virtual functions (VFs) for each physical function. Both of the physical function and the virtual function can provide an interface function as an I/O device. It is also possible that the physical function is devoted to set and manage virtual functions and that only the virtual function provides an interface function. In this specification, a port which is an interface provided by a virtual function will be referred to as a virtual port.
An apparatus in conformity with the MR-IOV specification includes, for example, multiple root complexes (hereinafter “RCs”) to which a processor is connected respectively, multiple root ports (hereinafter “RPs”) which the RCs include, multiple EPs which are to be starting points for input/output of data, and multiple switches for connecting the RPs and EPs. Each EP is configured so that it can provide its function (a data transfer function of transferring inputted data to another device) for each of processors accessing the EP via the RPs (so that the processor can control data transfer on the EP). The multiple processors can share each EP due to such a configuration. Each processor can independently access the EP via the RPs (each can independently control data transfer on the EP). Thereby, the multiple processors can independently execute data transfer without increase in the number of the EPs, and the performance of the data transfer process is enhanced.
In the MR-IOV, a tree-shaped topology constituted by one RP, and one or more EPs and switches logically connected to the RP is referred to as a “virtual hierarchy” (hereinafter “VH”). In a communication network in conformity with the MR-IOV (hereinafter an “MR-IOV network”), there exist the same number of VHs as the number of multiple RPs existing in the MR-IOV network.
One VH indicates an address space for data transfer controlled by a processor for each RP. For example, suppose that there exist a first VH constituted by an RP1, an EP1 and an EP2, and a second VH constituted by an RP2, the EP1 and the EP2 in an MR-IOV network. It is assumed that the RP1 is provided for an RC1 to which a processor 1 is connected, and the RP2 is provided for an RC2 to which a processor 2 is connected. In this case, the processor 1 and the processor 2 can independently control data transfer from the EP1 to the EP2 (or vice versa) via the RP1 on the first VH and via the RP2 on the second VH, respectively.
One EP can implement both of the MR-IOV and the SR-IOV. In this case, the function of the SR-IOV is implemented for each of VHs supported by the EP. That is, an EP compatible with both of the MR-IOV and the SR-IOV includes a physical function and multiple virtual functions related thereto for each VH. Furthermore, the EP compatible with both of the MR-IOV and the SR-IOV can support VF migration for migrating a virtual function between VHs. Since the VF migration can be applied to load balancing between VHs, enhancement of the performance of a storage apparatus can be expected by implementing an EP supporting the VF migration in an internal network of a storage controller.
PTL 1 described below discloses a technique for migrating a virtual function between physical functions in an EP compatible with the SR-IOV. NPL 1 described blow discloses a technique about the VF migration in an EP compatible with the MR-IOV.
Citation List
Patent Literature
    PTL 1: JP Patent Publication (Kokai) No. 2008-152786 ANon Patent Literature    NPL 1: “Multi-Root I/O Virtualization and Sharing Specification, Revision 1.0, Section 3.2.4”; 2008; Author: PCI-SIG; pp. 104 to 107